Early-onset Failure Detection
Package-level Design Insight
Improving PCB Design Reliability Test
Our HRIT (High-Reliability Interconnect Test) Platform is an intuitive application that allows users to define thermal profiles and control the execution of oven cycling. This platform was developed to improve early-onset failure detection in PCB design reliability tests.
The HRIT Platform allows monitorization of PCB path impedance at desired points through the thermal cycle. Followed by logging and graphing data versus cycle for the test duration.
Making Sense of Your Data
When it comes to data, more isn’t always better. Data overload and siloed data can muddy the road to tangible improvements. The HRIT is equipped to help users make sense of the added insight gained within this application. This is done through a database of PCB features and performance that is maintained for correlation and analysis.
Charting the best performance features of the PCB design is simplified with the HRIT. Users can define UUT features of interest for performance tracking. One example of this time-saving capability is impedance data reports which can be used to detect early-onset failure or crack growth.
Now that you’ve made sense of your data, utilize the HRIT to develop a predictive model. Platform capabilities include user-defined data presentations which draw from four dimensions of test design to identify effects of interest, a wide range of analysis parameters, and enhanced sensitivity and statistical modeling.
Users can compare with other Package/Pitch/Routes to assess manufacturability. Subsequently, open failures can be fed to a two-parameter Weibull analysis for predictive modeling.
This platform has been deployed in assessing new PCB design reliability, with an emphasis on high PCB layer count. This deployment involved evolving design requirements with varied characteristics and multiple BGA sites.
As a result, needs for this process included characterizing reliability of various PCB design aspects, tracking and correlating degradation of performance, and quantifying with data the most robust/highest performing designs to provide rationale for design selection.